GaN HEMT Knowledge Base
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Transport, high-field physics, and breakdown

The current path is fast and dense, but the highest field near the drain-side gate edge drives many limits.

Last updated: 2026-05-11 · static LLM wiki

Low-field and RF transport

At low lateral field, current is set by 2DEG density, mobility, access resistance, and contact resistance. Mobility is limited by polar optical phonons, interface roughness, alloy disorder, dislocations, charged traps, remote surface charges, and background impurities.

For RF devices, short gate length, high transconductance, low capacitance, and high saturation velocity drive high fT and fmax. But RF output power and linearity are often limited by trapping/current collapse and self-heating, not just intrinsic channel speed.

High-field region

Drain-side gate-edge field crowding

AlGaN barrier GaN channel / buffer SourceGateDrain field plate field spread by plate peak field near drain-side gate edge hot carriers can inject into traps

Peak electric field occurs near the drain-side gate edge. A field plate spreads the field but adds capacitance.

The highest field usually occurs near the drain-side gate edge. That region controls hot-electron injection, gate leakage, field crowding, electroluminescence, dynamic RON, and off-state degradation. Field plates spread the electric field over a larger region, improving breakdown and reducing peak field, but they add capacitance and can slow RF/switching performance.

Breakdown is usually extrinsic

GaN’s intrinsic breakdown field is high, but real lateral HEMTs often fail through surface leakage, buffer leakage, punch-through, gate-edge field crowding, substrate leakage, trap-assisted conduction, thermal runaway, or imperfect passivation. The design tradeoff is straightforward: increasing gate-drain spacing and field-plate length improves voltage capability but increases device area, capacitance, and RON.

Design knobs

  • Gate-drain spacing and field-plate geometry.
  • Carbon/iron-doped buffers to suppress leakage, balanced against trap memory effects.
  • Back barriers and superlattice buffers to improve confinement and isolation.
  • Surface treatments and passivation to suppress surface leakage/trapping.
  • Substrate choice and package design for heat removal.