GaN HEMT Knowledge Base
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Traps, current collapse, and reliability

The central practical problem: charge gets trapped during stress and changes the channel later.

Last updated: 2026-05-11 · static LLM wiki

What traps do

Trap-induced current collapse

AlGaN barrier / surface GaN channel C/Fe-doped buffer 2DEG partially depleted −−− surface traps −−− buffer traps Trapped negative charge raises local channel potential → current collapse / dynamic RON

Surface and buffer traps store negative charge after stress, locally depleting the 2DEG and raising dynamic on-resistance.

Under high drain bias, RF swing, or switching stress, electrons can be captured by surface, barrier, interface, dielectric, or buffer traps. Trapped negative charge depletes the 2DEG locally. The visible result is current collapse, gate lag, drain lag, or increased dynamic RON after stress.

This is why a GaN HEMT can look excellent in DC curves but worse under pulsed or real switching conditions.

Trap locations

  • Surface states: especially between gate and drain; passivation quality matters.
  • Barrier/interface traps: AlGaN/GaN interface and barrier defects modulate channel charge.
  • Buffer traps: carbon or iron compensation reduces leakage but can introduce slow memory effects.
  • Gate dielectric traps: central to MIS-HEMT hysteresis, threshold drift, and TDDB.
  • p-GaN gate defects: Mg-related defects, hole dynamics, and gate-stack conduction paths affect E-mode reliability.

Characterization

Trap characterization uses pulsed I–V, gate-lag/drain-lag measurements, dynamic RON, transient spectroscopy, conductance methods, C–V hysteresis, electroluminescence, temperature-dependent stress/recovery, and increasingly application-like switching tests.

JEDEC has added GaN-specific methods such as JEP173 for dynamic on-resistance, JEP180/JEP182 for switching reliability, and JEP186 for transient off-state robustness. These exist because static silicon-style tests do not capture GaN’s fast-switching stress and trap memory well enough.

Mitigation

  • Passivation and surface pretreatment to reduce surface states.
  • Field plates to reduce peak electric field.
  • Cleaner epitaxy and lower defect density.
  • Optimized buffer doping that balances leakage suppression against trapping.
  • Gate stacks with lower interface and border-trap density.
  • Qualification under actual mission waveforms, not just DC stress.